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1 document # sram112 rev a revised october 2005 description the p4c188 and p4c188l are 65,536-bit ultra high speed static rams organized as 16k x 4. the cmos memories require no clocks or refreshing and have equal access and cycle times. inputs and outputs are fully ttl-compatible. the rams operate from a single 5v10% tolerance power supply. with battery backup, data integrity is maintained for supply voltages down to 2.0v. current drain is typically 10 a from a 2.0v supply. single 5v10% power supply data retention with 2.0v supply (p4c188l military) three-state outputs ttl/cmos compatible outputs fully ttl compatible inputs standard pinout (jedec approved) ? 22-pin 300 mil dip ? 24-pin 300 mil soj ? 22-pin 290 x 490 mil lcc features full cmos, 6t cell high speed (equal access and cycle times) ? 10/12/15/20/25 ns (commercial) ? 12/15/20/25/35 (industrial) ? 15/20/25/35/45 ns (military) low power (commercial/military) ? 715 mw active ? 12/15 ? 550/660 mw active ? 20/25/35/45 ? 193/220 mw standby (ttl input) ? 83/110 mw standby (cmos input) p4c188 ? 15 mw standby (cmos input) (p4c188l military) functional block diagram pin configurations p4c188/p4c188l ultra high speed 16k x 4 static cmos rams dip (p3, d3, c3) lcc (l3) for soj pin configuration, please see end of datasheet. access times as fast as 10 nanoseconds are available, permitting greatly enhanced system speeds. cmos is utilized to reduce power consumption to a low 715mw active, 193mw standby and only 5mw in the p4c188l version. the p4c188 and p4c188l are available in 22-pin 300 mil dip, 24-pin 300 mil soj and 22-pin lcc packages provid- ing excellent board level densities.
p4c188/188l page 2 of 12 document # sram112 rev a maximum ratings (1) symbol parameter value unit v cc power supply pin with ?0.5 to +7 v respect to gnd terminal voltage with ?0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ?55 to +125 c symbol parameter value unit t bias temperature under ?55 to +125 c bias t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma recommended operating temperature and supply voltage industrial commercial grade(2) ambient temperature gnd v cc ?40c to +85c 0c to +70c 0v 0v 5.0v 10% 5.0v 10% 0v 5.0v 10% ?55c to +125c military symbol c in c out parameter input capacitance output capacitance conditions v in = 0v v out = 0v 5 7 unit pf pf capacitances (4) v cc = 5.0v, t a = 25c, f = 1.0mhz n/a = not applicable dc electrical characteristics over recommended operating temperature and supply voltage (2) notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. typ. i sb standby power supply current (ttl input levels) ce v ih mil. v cc = max ., ind./com?l. f = max., outputs open ___ ___ 40 35 ___ ___ ___ ___ 20 15 40 n/a 2.7 n/a ma ma ___ ___ ce v hc mil. v cc = max., ind./com?l. f = 0, outputs open v in v lc or v in v hc standby power supply current (cmos input levels) i sb1 symbol v ih v il v hc v lc v cd v ol v oh i li i lo parameter input high voltage input low voltage cmos input high voltage cmos input low voltage input clamp diode voltage output low voltage (ttl load) output high voltage (ttl load) input leakage current output leakage current test conditions v cc = min., i in = 18 ma i ol = +8 ma, v cc = min. i oh = ?4 ma, v cc = min. v cc = max. mil. v in = gnd to v cc com?l. v cc = max., ce = v ih , mil. v out = gnd to v cc com?l. p4c188 min 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?10 ?5 ?10 ?5 max v cc +0.5 0.8 v cc +0.5 0.2 ?1.2 0.4 +10 +5 +10 +5 p4c188l min max 2.2 ?0.5 (3) v cc ?0.2 ?0.5(3) 2.4 ?5 n/a ?5 n/a v cc +0.5 0.8 v cc +0.5 0.2 0.4 ?1.2 +5 n/a +5 n/a unit v v v v v v v a a
p4c188/188l page 3 of 12 document # sram112 rev a *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il data retention characteristics (p4c188l military temperature only) symbol v dr i ccdr t cdr t r ? parameter v cc for data retention data retention current chip deselect to data retention time operation recovery time test conditions ce v cc ?0.2v, v in v cc ?0.2v or v in 0.2v min 2.0 0 t rc typ.* v cc = 2.0v 3.0v 10 15 max v cc = 2.0v 3.0v 600 900 unit v a ns ns data retention waveform *t a = +125c t rc = read cycle time ? this parameter is guaranteed but not tested. i cc symbol parameter temperature range dynamic operating current* commercial industrial military ?10 n/a ?12 ?15 ?20 ?25 ?35 ?45 unit n/a ma ma ma power dissipation characteristics vs. speed n/a 150 155 160 170 180 n/a 170 160 155 150 145 180 170 160 155 150 n/a n/a
p4c188/188l page 4 of 12 document # sram112 rev a ac characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) notes: 5. ce is low and we is high for read cycle. 6. we is high, and address must be valid prior to or coincident with ce transition low. 7. transition is measured 200mv from steady state voltage prior to change with specified loading in figure 1. this parameter is sampled and not 100% tested. 8. read cycle time is measured from the last valid address to the first transitioning address. timing waveform of read cycle no. 2 (6) timing waveform of read cycle no. 1 (5) sym. t rc t aa t ac t oh t lz t hz t pu t pd parameter read cycle time address access time chip enable access time output hold from address change chip enable to output in low z chip disable to output in high z chip enable to power up time chip disable to power down time -10 min 10 2 2 0 max 10 10 5 10 -12 min 12 2 2 0 max 12 12 6 12 -15 min 15 2 2 0 max 15 15 6 15 -20 min 20 2 3 0 max 20 20 8 20 -25 min 25 2 3 0 max 25 25 10 25 -35 min 35 2 3 0 max 35 35 20 35 -45 min 45 2 3 0 max 45 45 25 45 unit ns ns ns ns ns ns ns ns
p4c188/188l page 5 of 12 document # sram112 rev a 12. transition is measured 200mv from steady state voltage prior to change with specified loading in figure 1. this parameter is sampled and not 100% tested. notes: 9. ce and we must be low for write cycle. 10. if ce goes high simultaneously with we high, the output remains in a high impedance state. 11. write cycle time is measured from the last valid address to the first transition address. timing waveform of write cycle no. 1 ( we we we we we controlled) (9) ac characteristics - write cycle (v cc = 5v 10%, all temperature ranges) (2) sym. parameter -10 -12 -15 -20 -25 -35 -45 unit min min min min min min min max max max max max max max t wc t cw t aw t as t wp t ah t dw t dh t wz t dw write cycle time chip enable time to end of write address valid to end of write address set-up time write pulse width address hold time from end of write data valid to end of write data hold time write enable to output in high z output active from end of write 10 7 7 0 8 0 5 0 2 5 12 8 8 0 9 0 6 0 2 6 13 10 10 0 10 0 7 0 2 6 20 13 15 0 13 0 8 0 2 8 25 15 20 0 15 0 10 0 2 35 25 25 0 25 0 15 0 3 15 45 35 35 0 35 0 20 5 3 20 ns ns ns ns ns ns ns ns ns ns 10
p4c188/188l page 6 of 12 document # sram112 rev a timing waveform of write cycle no. 2 ( ce ce ce ce ce controlled) (9) input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 mode ce ce ce ce ce we we we we we output power standby h x high z standby read l h d out active write l l d in active * including scope and test fixture. note: because of the ultra-high speed of the p4c188/l, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.73v (thevenin voltage) at the comparator input, and a 116 ? resistor must be used in series with d out to match 166 ? (thevenin resistance). figure 1. output load figure 2. thevenin equivalent ac test conditions truth table
p4c188/188l page 7 of 12 document # sram112 rev a ordering information 1513 10 10 12 15 20 25 35 45 plastic dip -10pc -12pc -15pc -20pc -25pc -35pc 45pc plastic soj -10jc -12jc -15jc -20jc -25jc -35jc -45jc industrial plastic dip n/a -12pi -15pi -20pi -25pi -35pi -45pi plastic soj n/a -12ji -15ji -20ji -25ji -35ji -45ji side brazed dip n/a n/a -15cm -20cm -25cm -35cm -45cm cerdip n/a n/a -15dm -20dm -25dm -35dm -45dm lcc n/a n/a -15lm -20lm -25lm -35lm -45lm side brazed dip n/a n/a -15cmb -20cmb -25cmb -35cmb -45cmb cerdip n/a n/a -15dmb -20dmb -25dmb -35dmb -45dmb lcc n/a n/a -15lmb -20lmb -25lmb -35lmb -45lmb speed (ns) military temperature military processed* temperature range package commercial selection guide the p4c188/l is available in the following temperature, speed and package options. the p4c188l is only available over the military temperature range. * military temperature range with mil-std-883, class b processing. n/a = not available
p4c188/188l page 8 of 12 document # sram112 rev a soj pin configuration soj (j4)
p4c188/188l page 9 of 12 document # sram112 rev a pkg # # pins symbol min max a 0.100 0.200 b 0.014 0.023 b2 0.030 0.060 c 0.008 0.015 d 1.050 1.260 e 0.260 0.310 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - c3 22 (300 mil) 0.300 bsc 0.100 bsc pkg # # pins symbol min max a - 0.225 b 0.015 0.020 b2 0.045 0.065 c 0.009 0.012 d 1.060 1.110 e 0.290 0.320 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - 0 15 d3 22 (300 mil) 0.300 bsc 0.100 bsc side brazed dual in-line package cerdip dual in-line package
p4c188/188l page 10 of 12 document # sram112 rev a pkg # # pins symbol min max a 0.128 0.148 a1 0.082 - b 0.016 0.020 c 0.007 0.010 d 0.620 0.630 e e e1 0.292 0.300 e2 q0.025- j4 24 (300 mil) 0.050 bsc 0.267 bsc 0.335 bsc pkg # # pins symbol min max a 0.060 0.080 a1 0.050 0.068 b1 0.022 0.028 d 0.284 0.296 d1 d2 d3 - 0.296 e 0.484 0.496 e1 e2 e3 - 0.496 e h j l 0.039 0.051 l1 0.039 0.051 l2 0.058 0.072 nd ne l3 22 0.150 bsc 0.075 bsc r = .012 4 7 0.300 bsc 0.150 bsc 0.050 bsc r = .012 soj small outline ic package rectangular leadless chip carrier
p4c188/188l page 11 of 12 document # sram112 rev a pkg # # pins symbol min max a - 0.210 a1 0.015 - b 0.014 0.022 b2 0.045 0.070 c 0.008 0.014 d 1.145 1.165 e1 0.240 0.280 e 0.300 0.325 e eb - 0.430 l 0.115 0.150 0 15 0.100 bsc p3 22 (300 mil) plastic dual in-line package
p4c188/188l page 12 of 12 document # sram112 rev a revisions document number : sram112 document title : p4c188 / p4c188l ultra high speed 16k x 4 static cmos rams rev. issue date orig. of change description of change or 1997 dab new data sheet a oct-05 jdb change logo to pyramid

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